xilinx board
赛灵思开发板
xilinx tools
赛灵思工具
xilinx fpga
赛灵思fpga
xilinx chip
赛灵思芯片
xilinx design
赛灵思设计
xilinx support
赛灵思支持
using xilinx
使用赛灵思
install xilinx
安装赛灵思
configure xilinx
配置赛灵思
tested xilinx
已测试赛灵思
we used a xilinx fpga to accelerate real-time video processing on the edge device.
我们使用赛灵思fpga加速边缘设备上的实时视频处理
the engineer downloaded the xilinx vivado toolchain to synthesize and implement the design.
工程师下载了赛灵思vivado工具链来综合并实现该设计
our prototype runs on a xilinx zynq soc with linux controlling custom logic.
我们的原型运行在赛灵思zynq片上系统上由linux控制自定义逻辑
she integrated a xilinx ip core for axi interconnect to simplify the system architecture.
她集成了赛灵思ip核用于axi互连以简化系统架构
the team validated timing closure on the xilinx device before the final build.
团队在最终构建前在赛灵思器件上完成了时序收敛验证
we migrated the project to a newer xilinx fpga family to meet bandwidth requirements.
我们将项目迁移到更新的赛灵思fpga系列以满足带宽需求
he checked the xilinx datasheet to confirm the transceiver line rate limits.
他查阅赛灵思数据手册以确认收发器线速率限制
the driver targets a xilinx pcie endpoint for high-throughput data capture.
该驱动面向赛灵思pcie端点用于高吞吐数据采集
they configured the xilinx clocking wizard to generate stable reference clocks.
他们配置赛灵思时钟向导以生成稳定的参考时钟
our ci pipeline runs xilinx synthesis jobs overnight to catch regressions early.
我们的持续集成流水线在夜间运行赛灵思综合任务以尽早发现回归
the board uses xilinx ddr controllers to maximize memory performance for the workload.
该板卡使用赛灵思ddr控制器以最大化工作负载的内存性能
she opened a xilinx support ticket after encountering an implementation crash.
她在遇到实现阶段崩溃后提交了赛灵思支持工单
xilinx board
赛灵思开发板
xilinx tools
赛灵思工具
xilinx fpga
赛灵思fpga
xilinx chip
赛灵思芯片
xilinx design
赛灵思设计
xilinx support
赛灵思支持
using xilinx
使用赛灵思
install xilinx
安装赛灵思
configure xilinx
配置赛灵思
tested xilinx
已测试赛灵思
we used a xilinx fpga to accelerate real-time video processing on the edge device.
我们使用赛灵思fpga加速边缘设备上的实时视频处理
the engineer downloaded the xilinx vivado toolchain to synthesize and implement the design.
工程师下载了赛灵思vivado工具链来综合并实现该设计
our prototype runs on a xilinx zynq soc with linux controlling custom logic.
我们的原型运行在赛灵思zynq片上系统上由linux控制自定义逻辑
she integrated a xilinx ip core for axi interconnect to simplify the system architecture.
她集成了赛灵思ip核用于axi互连以简化系统架构
the team validated timing closure on the xilinx device before the final build.
团队在最终构建前在赛灵思器件上完成了时序收敛验证
we migrated the project to a newer xilinx fpga family to meet bandwidth requirements.
我们将项目迁移到更新的赛灵思fpga系列以满足带宽需求
he checked the xilinx datasheet to confirm the transceiver line rate limits.
他查阅赛灵思数据手册以确认收发器线速率限制
the driver targets a xilinx pcie endpoint for high-throughput data capture.
该驱动面向赛灵思pcie端点用于高吞吐数据采集
they configured the xilinx clocking wizard to generate stable reference clocks.
他们配置赛灵思时钟向导以生成稳定的参考时钟
our ci pipeline runs xilinx synthesis jobs overnight to catch regressions early.
我们的持续集成流水线在夜间运行赛灵思综合任务以尽早发现回归
the board uses xilinx ddr controllers to maximize memory performance for the workload.
该板卡使用赛灵思ddr控制器以最大化工作负载的内存性能
she opened a xilinx support ticket after encountering an implementation crash.
她在遇到实现阶段崩溃后提交了赛灵思支持工单
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